Three-dimensional circuit integration by stacking integrated circuits in multiple tiers allows circuit designers to achieve benefits of improved power, performance, area and cost (PPAC) beyond the Moore's law scaling limit. Various schemes of three-dimensional integrated circuit (3D IC) stacking, including silicon-in-package (SiP) 3D IC stacking schemes such as wire-bond, flip-chip bond, through-silicon via (TSV) and silicon interposer technologies have been developed in order to achieve higher densities in circuitry, inter-tier links and vias. 3D ICs with multi-tier stacking are desirable in devices in which form factor requirements are stringent, such as smartphones and other mobile devices. In addition to conventional SiP 3D IC stacking schemes, sequential monolithic 3D IC (sM3DIC) technology has been developed. In sM3DIC, a single crystal semiconductor layer is sequentially integrated and bonded onto a finished lower-tier complementary metal oxide semiconductor (CMOS) wafer, and an upper-tier CMOS is then built upon it.
The sM3DIC technology is currently considered to have the potential of achieving huge PPAC benefits with high inter-tier link/via densities, on the order of more than 1,000,000 links per square millimeter. However, the sM3DIC technology currently faces several significant process integration challenges that need to be overcome before it can become commercially feasible. Such challenges may include, for example, low thermal budget/process requirements for upper-tier source/drain (S/D) ohmic contact, channel/well dopant activation, S/D recrystallization, and potential contamination problems related to copper interconnect processes when the lower-tier wafer completed by a back end-of-line (BEOL) process is brought to the front end-of-line (FEOL).
Another 3D IC stacking scheme, called parallel monolithic 3D IC (pM3DIC), may be capable of achieving inter-tier link/via densities on the order of about 100,000 to 1,000,000 links per square millimeter. In pM3DIC, a wafer-to-wafer (W2W) hybrid bonding (metal-to-metal and oxide-to-oxide fusion bonding) technique is used which includes a high-precision W2W alignment process having a tolerance of less than 0.5 μm in combination with a very thin upper-tier wafer having a thickness of less than 5 μm after removal of the bulk silicon. The high-precision W2W alignment process allows the landing pad size to be reduced while the very thin upper-tier wafer allows the size of through-silicon and through-oxide inter-tier vias to be reduced, thereby achieving an increase the inter-tier link/via density.
Even though the pM3DIC approach is currently considered to be capable of offer an intermediate level of inter-tier link/via density within a shorter development period, significant process challenges may still exist. For example, while it is possible to thin the upper-tier wafer down to 5 μm or less by using existing wafer thinning techniques, such as mechanical wafer backgrinding including a coarse grinding and a fine polish followed by chemical-mechanical polish (CMP), CMOS device characteristics are found to drift when the wafer is thinned down to 25 μm or less due to particle-induced stress impact onto the CMOS device during the mechanical grinding process in the bumping line. Moreover, with existing mechanical wafer grinding and CMP technologies, it may still be difficult to achieve a reasonable total thickness variation (TTV) of 1 μm or less.
Another approach for wafer thinning for a CMOS imager utilizes selective wet etch on a P+ etch stop layer. However, such an approach may present challenges for obtaining a reasonable process window to control precise and uniform layer thickness, to control defect density, and to manage boron doping diffusion during the remaining CMOS process. Alternatively, a silicon-on-insulator (SOI) wafer may provide an acceptable solution for precise wafer thinning down to the “buried oxide” (BOX) layer, that is, a layer including a silicon (Si) layer and a silicon dioxide (SiO2) layer processed by coarse and fine grinding, followed by CMP, and then followed by selective wet etch of Si and SiO2. The SOI wafer may be used as the starting wafer for the upper-tier. However, once the wafer is processed by mechanical grinding through the bumping line, the wafer may often be contaminated with heavy metals such as gold, silver, tin, or other metals in practice. With heavy metal contamination, the wafer can no longer be practically processed in the BEOL to add additional backside metals with fine pitch metal layers, thus losing 3D integration flexibility in terms of interconnect configurations. Moreover, other factors such as wafer cost, material utilization, and throughput considerations, for example, may not be favorable for pM3DIC integration.